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`timescale 1ns/1ps
module main;
reg clk = 0;
always #1 clk = ~clk;
reg go = 0;
reg rst = 1;
reg [7:0] i_data = 8'hAA;
wire [7:0] o_data;
wire busy;
wire spi_clk;
wire spi_mosi;
reg spi_miso = 0;
spi_controller dut(
.clk(clk), .rst(rst), .go(go /*& ~busy*/),
.i_data(i_data), .o_data(o_data),
.busy(busy),
.spi_clk(spi_clk),
.spi_mosi(spi_mosi),
.spi_miso(spi_miso));
initial begin
$dumpfile("main.vcd");
$dumpvars(2, main);
//$display("Hello world!");
//$monitor("T%03d | clk: %0d", $time, clk);
#2 rst = 0;
go = 1;
#2 go = 0;
#3 spi_miso = 1;
#4 spi_miso = 0;
#4 spi_miso = 1;
#4 spi_miso = 0;
#4 spi_miso = 1;
#4 spi_miso = 0;
#4 spi_miso = 1;
#4 spi_miso = 0;
#4 spi_miso = 1;
#4 spi_miso = 0;
#4 spi_miso = 1;
#32 $finish;
end
initial begin
#34 i_data = 8'h55;
go = 1;
#2 go = 0;
end
endmodule
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